1. Field of the Invention
The present invention relates generally to an imaging device and more particularly to a solid-state imaging device comprising a plurality of photoelectric conversion elements integrated on a semiconductor substrate.
2. Description of the Related Art
The solid-state imaging device has numerous advantageous features such as reduced size, light weight, freedom from maintenance, elongated uselife and others which are excellent over those of the image pick-up tube. Being backed up by the remarkable progress in the semiconductor technology, the solid-state imaging device is now developed to such a state as to replace the image pick-up device from the stand point of the manufacturing costs as well as performance.
The solid-state imaging device can be generally classified into two categories, i.e. the MOS type solid-state imaging device in which signal charges generated by photoelectric conversion elements (such as photodiodes or the like) are read out over aluminum signal lines through MOS transistors and the CCD type solid-state imaging device in which photoelectric charges generated by the individual photoelectric conversion elements are read out through CCD (abbreviation of Charge Coupled Device) shift registers. The CCD type solid-state imaging device in turn can be classified into three types, that is, a frame transfer type CCD imaging device which includes light-receiving or light-sensitive parts and charge storage parts separately from each other, an interline type CCD solid-state imaging device having stripe-like charge storage parts and charge transfer parts between light-sensitive pixels (or picture elements), and a FIT (Frame Interline Transfer) type CCD imaging device which is a hybrid of the frame transfer type and interline type device. These types of CCD solid-state imaging devices enjoy an advantageous feature in that the photoelectric signal charges generated by the photoelectric elements can be outputted with high efficiency, whereby noise generation can be reduced significantly as compared with the MOS type imaging device.
A typical one of the CCD solid-state image device is disclosed in ISSCC 82, pp. 168-169 and ISSCC 86, pp. 94-95.
For having a better understanding of the present invention, an interline type CCD solid-state imaging device known heretofore will be described in some detail by referring to FIGS. 1 and 2 of the accompanying drawings, in which FIG. 1 shows a structure of the hitherto known interline type CCD solid-state imaging device.
Referring to FIG. 1, each of photoelectric conversion elements 1 is constituted by a photodiode implemented in the form of a pn-junction diode. The element 1 converts photoelectrically the light incident thereon into photoelectric signal charge and stores the charge therein. These photoelectric conversion elements are disposed in vertical and horizontal arrays in a regular matrix-like configuration. Vertical CCD registers 3 are provided for the vertical rows of the photoelectric conversion elements in one-to-one correspondence for shifting or transferring electric charges in the vertical direction. A select gate 2 is provided between each of the photoelectric conversion elements and the associated one of the vertical CCD registers 3 for the purpose of controlling the signal charge flow from the photoelectric conversion element to the associated vertical CCD register 3. A horizontal CCD register 4 are provided at one ends of the vertical CCD registers 3 for receiving in parallel the signal charges transferred through the individual vertical CCD registers 3 to thereby transfer the received charges in the horizontal direction. An output amplifier 5 is provided at one end of the horizontal CCD register 4 for amplifying the signal charges transferred the horizontal CCD register 4.
The photoelectric signal charge stored in the photoelectric conversion element 1 is transferred to the associated vertical CCD register through the select gate 2. The signal charge thus selected is then transferred to the output amplifier 5 through the vertical CCD register 3 and horizontal CCD register 4 to be finally outputted from through the output amplifier 5 as the image (video) signal.
The vertical CCD register 3 is usually driven by a four-phase clock signal. Accordingly, four phase clock wires 6 to 9, 10 to 13, 14 to 17 are connected to the vertical CCD registers 3, wherein the clock wires for two phases 7; 9; 11; 13 and 15; 17 serve also as gate wires for the select gates 2.
Operation of the vertical CCD registers 3 of the imaging device will be explained by referring to FIGS. 2A and 2B of the accompanying drawings, wherein FIG. 2A is a sectional view of the vertical CCD register 3 taken along a line A--A' in FIG. 1 and FIG. 2B shows time charts for illustrating charges in potential in the vertical CCD register 3 as a function of time. Upon application of the clock pulses .phi..sub.V2 and .phi..sub.V4 onto the clock wires (gate wires) 11, 13, 15 and 17, photoelectric signal charges Q.sub.3, Q.sub.4, Q.sub.5 and Q.sub.6 stored in the photodiodes 1 are transferred to areas underlying the gate electrodes of the associated vertical registers 3, respectively. At a time point t.sub.2, the clock pulse .phi..sub.V3 is applied onto the clock wires 12 and 16, resulting in that the photoelectric signal charges Q.sub.3 and Q.sub.4 on one hand and the photoelectric signal charges Q.sub.5 and Q.sub.6 on the other hand are mixed together into photoelectric signal charges (Q.sub.3 +Q.sub. 4) and (Q.sub.5 +Q.sub.6), respectively. Subsequent successive applications of the clock pulses at time points t.sub.3, t.sub.4 and t.sub.5 in the similar manner result in that the photoelectric signal charges (Q.sub.1 +Q.sub.2), (Q.sub.3 +Q.sub.4) and (Q.sub.5 +Q.sub.6) resulting from the mixing are sequentially transferred in the vertical direction. The photoelectric signal charges transferred in this manner are outputted to the output amplifier 5 sequentially through the horizontal CCD register 4 during the vertical scan period. Upon completion of the transfer of all the signal charges present in the vertical CCD register 3, then the photoelectric signal charges stored in the individual photodiodes 1 are again transferred to the vertical CCD registers 3, whereby the similar process described above is repeated. As will now be seen, the signal storage period in the hitherto known imaging device corresponds to the time required for the signal charges to be transferred through the vertical CCD register 3, i.e. the time equal to one field period.
In the solid-state imaging device known heretofore, the number of the signal charges which can be transferred through the vertical CCD register is limited by the number of transfer electrodes of the vertical CCD register and phase number of the clock pulse signal. Consequently, the signal storage time of the photodiode remains constant, whereby a problem arises that the signal charge storage time or duration can not be controlled freely, making it impossible to implement the electronic shutter function and others.